1. Field of the Invention
The present invention generally relates to semiconductor devices and fabrication methods of the same, and more particularly, to a power control transistor having a vertical structure and a method of fabricating the same.
2. Description of the Related Art
The power control transistors are widely used in various fields such as home electric appliances, electric railways, electric automobiles and electric power. The power control transistors are required to have high breakdown capability such that dielectric breakdown does not take place even if high power is applied. The power control transistors are also required to have a small on-state resistance in order to realize low insertion loss. Recently, transistors having a vertical structure have had a great deal of attention as power control transistors.
FIG. 1 is a cross-sectional view of a Si-based vertical type MOSFET (hereinafter referred to as first prior art). An n-type SiC buffer layer 12 and n-type SiC channel layer 14 are laminated on an n-type SiC substrate 10 in this order. A gate oxide film 54 is formed on the channel layer 14, and a gate electrode 62 is provided on the gate oxide film 54. Source electrodes 62 are provided on opposing sides of the gate electrode 60. N-type regions 52 are respectively provided below the source electrodes 60, and are surrounded by p-type regions 50. A drain electrode (not shown) is provided on the backside of the SiC substrate 10.
Japanese Patent Application Publication No. 2004-165520 discloses, in FIG. 1, a vertical FET using a GaN-based semiconductor (hereinafter referred to as second prior art). On a substrate, laminated are an undoped GaN layer, an n-type GaN drain layer, an n-type GaN channel layer, and an n-type GaN source layer in this order. An opening that reaches the drain layer is provided in a given region, and an insulating film is provided on a sidewall of the opening. A gate electrode is provided an insulating film on the channel layer. A source electrode and a drain electrode are respectively provided for the source layer and the drain layer.
However, the first prior art has a problem such that the SiC channel layer realizes a mobility of only tens of cmV/s and the resultant on-state resistance. is as low as tens of mΩ/cm2. The second prior art has a problem such that high breakdown voltage cannot be achieved-because the drain electrode is connected to the drain layer. If it is attempted to arrange the drain electrode on the backside of the substrate for improvement in breakdown, the substrate may be a GaN substrate, which has lattice match with the GaN layer. However, the GaN substrate is very expensive and has a difficulty in enlarging the size. For a substrate that does not have lattice match with the GaN layer, GaN cannot be grown to form a thick film, and high breakdown cannot be achieved.